# Portland Community College | Portland, Oregon

### CCOG for ENGR 171 archive revision 201403

You are viewing an old version of the CCOG. View current version »

Effective Term:
Summer 2014 through Summer 2016
Course Number:
ENGR 171
Course Title:
Introduction to Digital Logic Design
Credit Hours:
5
Lecture Hours:
40
Lecture/Lab Hours:
0
Lab Hours:
30

#### Course Description

Introduces analysis and computation of basic logic problems and circuits. Covers number systems, Boolean algebra, and logic circuit simplification techniques to produce simplified logic for minimal realization. Includes the creation of designs utilizing basic logic families, flip-flops, registers, and/or counters. Audit available.

#### Intended Outcomes for the course

Upon successful completion of this course, students will have be able to:

1. Manipulate Boolean expressions to create the minimum realizable expression or circuit.
2. Translate circuit descriptions, for example truth tables or timing diagrams, into combinatorial logic and/or MSI device circuits.
3. Utilize appropriate digital devices to create circuits with memory.

#### Course Activities and Design

Course activities will include lecture presentations, coordinated homework and laboratory assignments, design project, and examinations.

#### Outcome Assessment Strategies

Student evaluation includes examinations, laboratory assignments, homework assignments, design project, and a final comprehensive examination.  Specific evaluation procedures will be discussed during the first class meeting.

#### Course Content (Themes, Concepts, Issues and Skills)

Instructional Goals:
To become familiar with the number systems commonly used with digital
systems and to gain skill in converting numbers from one system to
others.
Objectives:
1.1  Number System Representation
1.1.1     Determine the weight of a digit given the position of the
digit and the base of the number system.
1.1.2     Count in a given number system.
1.2  Number System Conversions
1.2.1     Convert a binary,  BCD,  hexadecimal, or other radix number into its decimal equivalent.
1.2.2     Convert a decimal number into its binary, octal, BCD, hexadecimal, or other radix equivalent.

2.0  Basic logic gates and circuits
Instructional Goal:
To become familiar with the symbols, truth tables, and Boolean expressions for basic logic gates including AND, OR, NOT, NAND, NOR, and exclusive-OR logic gates.
Objectives:
2.1  Basic Logic Gates
2.1.1     Draw and identify the positive logic and the DeMorgan equivalent symbol for each of the basic logic gates.
2.1.2     Write the truth table for each basic logic gate.
2.1.3     Write a Boolean expression for the positive logic symbol and for the DeMorgan equivalent symbol for each basic logic gate.
2.1.4     Given the input signals (static and/or time- varying), determine the output signal for each basic logic gate.
2.2  Analyzing SSI Combinational Circuits
2.2.1     Given a schematic diagram for a combinational logic circuit containing mixed assertion levels, write a Boolean expression and a truth table for the circuit.
2.2.2     Given a schematic diagram using mixed logic and DeMorgan equivalent symbols, analyze the operation of the circuit by determining signals at all intermediate test points and circuit outputs.
2.2.3     Given a schematic diagram and an input-output timing diagram, determine the probable cause of the circuit malfunction, isolating the trouble to the gate level.
3.0  Logic family characters and device parameters
Instructional Goal:
Gain skill in using manufacturer data to determine specified parameters for digital ICs.
Objectives:
3 .1 Mechanical Characteristics
3.1.1     Determine the pin number of a specific pin on the integrated circuit package.
3.1.2     Determine the package type, e.g. ceramic dual-inline package.
3.1.3     Locate the part number and determine the function/part name, e.g. 7400 Quadruple 2-Input Positive-NAND Gate.
3.2  Electrical Characteristics
3.2.1     Define and determine the value of the following parameters for a specified device.
Supply voltage range
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
High-level input current
Low-level input current
High-level output current
Low-level output current
Operating free-air temperature
Supply current
3.2.2     Define and look-up the following switching parameters: low-to-high level output Propagation delay time; high-to-low level output propagation delay time.
3.2.3     Describe the operation of open collector and three state outputs.
3.2.3     Contrast the operating characteristics of major logic families:  TTL, LSTTL, ASTTL, ALSTTL, ECL, CMOS, HCMOS,  GaAs.
4.0  Boolean algebra
Instructional Goal:
Learn to simplify Boolean logic expressions using the rules of Boolean Algebra.
Objectives:
4.1  Boolean Algebra Rules
4.1.1     Know  the following Boolean identities
a.   A ¿ 0 = 0      A + 0 = A
b.   A ¿ 1 = A      A + 1 = 1
c.   A ¿ A = A      A + A = A
d.   A ¿ Not-A = 0       A + Not-A = 1
e.   A = Not-Not-A       Not-Not-A = A
f.   A ¿ (A + B) = A
g.   A + (Not-A ¿ B) = A + B
h.   AB = BA        A+B = B+A
i.   (AB)C=A(BC)         (A+B)+C = A+(B+C)
j.   AB+AC = A(B+C) (A+B)(A+C) = A + (B+C)
k.   A + AB = A          A + Not-A B = A + B
l.   AB + Not-A B = A + B
m.   A(A+B) = A
n.   A(Not-A + B) = AB
o.   Not-(AB) = Not-A + Not-B
p.   Not-(A+B) = Not-A Not-B

4.2  Simplification of Boolean Expressions
4.2.1     Use the identities in 5.1.1 to simplify Boolean expressions for up to four variables.
4.2.2     Use the identities in 5.1.1 to convert a sum of products  expression to a product of sums expression  or vice versa.
5.0  Synthesis of combinational logic circuits
Instructional Goal:
To learn to use Karnaugh maps to produce a simplified expression for a logic function and to implement the simplified expression with common logic gates.
Objectives:
5.1  Karnaugh Mapping
5.1.1     Draw and label Karnaugh Maps for up to 6 variables.
5.1.2     Properly place 1's and 0's in a map to represent a given Boolean function.
5.1.3     Properly group 1's to produce a minimal sum-of-products expression for the function.
5.1.4     Properly group 0's to produce a minimal product-of-sums expression for the function.
5.2  Designing Combinational Logic Circuits
5.2.1     Given a written problem description, develop a truth table describing the circuit's operation.
5.2.2     Use Boolean algebra or a Karnaugh map to produce a simplified sum-of-products or product-of-sums expression for  each output.
5.2.3     Design a circuit which implements the simplified functions with basic logic gates.
5.3  Timing of combinational logic circuits
5.3.1     Given input signal waveforms draw output waveforms which include the effects of gate propagation delays.
6.0   MSI combinational logic devices and circuits
Instructional Goals:
To become familiar with commonly available MSI combinational logic devices and how these devices are used in a variety of circuits.
Objectives:
6.1  Multiplexers/Demultiplexers
6.1.1     Describe the operation of a multiplexer and a demultiplexer and state the purpose of each pin on specified devices.
6.1.2     Read and interpret the truth tables and the dependency notation symbols for multiplexers and demultiplexers.
6.1.3     Analyze the operation and timing of a circuit using a multiplexer and/or demultiplexer.
6.1.4     Implement a Boolean function using a multiplexer.
6.2  Decoders
6.2.1     Describe the operation of a specified decoder and state the purpose of each pin on the device.
6.2.2     Read and interpret the function table and the dependency notation symbol for a decoder.
6.2.3     Design display circuits using decoder/drivers and seven-segment displays.
6.3  Encoder
6.3.1     Describe the function of a specified encoder and state the  purpose of each pin on the device.
6.3.2     Read and interpret the function table and dependency notation symbol for an encoder.
6.3.3     Design circuits using encoders.
7.0   Programmable logic devices
Instructional Goal:
To study the use of programmable logic devices commonly used to implement combinational logic functions.
Objectives:
7.1  General Characteristics of Programmable Logic Devices
7.1.1     Describe the internal structures of PROMs, FPLAs and PALs
7.1.2     Given the logic diagram for a PAL, determine the equation for the logic function being implemented.

7.1.3     Draw the fusemap needed to implement a simple function with a PAL.
7.1.4     Use a PAL data sheet to determine the device needed to implement a specified logic function.
7.1.5     Use a programmable logic software program such as ABEL to develop a fusemap which implements a combinational logic function in a PAL.
7.1.6     Program a PAL and verify its operation.
8.0  Latches and Flip-flops
Instructional Goal:
To learn the logic and timing characteristics of latches and flip-flops.
Objectives:
8.1  Latches
8.1.1     Draw the schematic diagram for an:
a.   RS latch
b.   Clocked RS latch
c.   D latch
8.1.2     Write a truth table for the circuit types listed under
8.1.1.
8.1.3     For each of the devices in 8.1.1 draw the output waveforms produced by given input waveforms.
8.1.4     For a D latch define the terms minimum pulse width, set-up time, and hold time.

8.2  Flip-flops
8.2.1     Draw the schematic symbols for D flip-flops and JK flip-flops.
8.2.2     Write a truth table for a D flip-flop and a truth table for a JK flip-flop.
8.2.3     Draw a timing diagram showing set-up and hold times for a  flip-flop.
8.2.4     Given a set of input signals to a flip-flop, show the output waveforms that will be produced.
8.2.5     Describe the conditions which may cause the output of a flip-flop to enter a metastable state.
9.0  Asynchronous counter circuits
Instructional Goal:
To use D-type and JK-type flip-flops to design and implement asynchronous counter circuits.
Objectives:
9.1  Counters made with SSI flip-flops

9.1.1     Design an n-bit ripple counter using D or JK flip-flops.
9.1.2     Draw the timing diagram for a n-bit ripple counter.
9.1.3     Describe the timing problems inherent in ripple counters.

9.2  Counters made with MSI components
9.2.1     Read and interpret data sheets for MSI counter devices.
9.2.2     Analyze a system using MSI counter circuits, e.g.,  digital
clock.
10.0  State machine circuits and devices
Instructional Goal:
To study the operation and applications of simple state machines such as
synchronous counters.
Objectives:
10.1 State machine analysis
10.1.1    Given the schematic for a synchronous state machine
circuit built with discrete flip-flops, analyze its
operation and determine the sequence of states that it
will step through when it is clocked.
10.2 State machine design
10.2.1    Given the characteristic table for a flip-flop,
determine the excitation table.
10.2.2    Design a synchronous state machine which sequences
through a given set of states using D or JK flip-flops.
10.2.3    Design a state machine which outputs a given set of
timing signals using a sequencer circuit with an
output decoder.
11.0  Design and documentation tools
Instructional Goal:
To develop skill in the design, documentation, and verification of a
complex combinational circuit.
Objectives:
11.1 Thoroughly document the development of a combinational logic
design project such as a 6-input 3-output circuit built with
discrete SSI devices.
11.1.1    Keep a design log showing all preliminary thinking,
design steps, simulation results, etc.
11.1.2    Use a word processor to produce the final report for
the project.

12.0  Lab skills
Instructional Goal:
To develop skill in using laboratory instruments, building and testing logic circuits.
Objectives:
12.1 Test and measurement equipment
12.1.1    Use a function generator to clock a logic circuit.
12.1.2    Use a frequency counter to measure the period and frequency of a signal.
12.1.3    Use an oscilloscope to:
a.  set the output voltage level for a function generator.
b.  determine the timing diagram for a logic circuit.
c.  determine the transfer curve for a logic gate.
d.  determine the truth table for a logic circuit.
12.1.4    Use a logic analyzer to:
a.  determine the truth table for a logic circuit.
b.  determine the timing diagram for a logic circuit.
12.2 Building and testing circuit
12.2.1    Build a logic circuit from a schematic diagram.
12.2.2    Connect the logic circuit to test and measurement
equipment to characterize the operation.