Course Content and Outcome Guide for MT 200 Effective Fall 2015
- Course Number:
- MT 200
- Course Title:
- Semiconductor Processing
- Credit Hours:
- Lecture Hours:
- Lecture/Lab Hours:
- Lab Hours:
- Special Fee:
Course DescriptionExplores aspects of semiconductor processing. Covers semiconductor device design (photo-voltaic cells, diodes, bipolar and MOSFET transistors) and the following manufacturing processes: oxidation, lithography, etch, doping, deposition, planarization, and test/sort. Prerequisites: MT 102, MT 103 or MT 104, MT 240, COMM 130 or COMM 215, or instructor permission. Audit available.
Addendum to Course Description
The focus of the student in this course is to explore a particular process used in semiconductor manufacturing, including process parameters, equipment configuration, logistics and issues in operation. The first half of the term will be lectures by the instructor on devices, circuits and manufacturing flows. The second half will be presentations based on student research. All students will be responsible for all material presented in class. Besides the course project, there will be weekly quizzes, one midterm, and a final exam.
Intended Outcomes for the course
Monitor and maintain device production by recognizing how they look and function in silicon planar technology, including: resistors, capacitors, diodes, PV cells, and MOSFET transistors
Monitor and maintain device production by following the manufacturing flows to create these devices
Develop increasing competence in an assigned production area by researching various aspects, such as: effects on device structure, relationship to process flow, resulting film properties, process mechanisms, effects of process inputs and settings, interactions between processes, equipment used, equipment options, process monitoring.
Enhance production and maintenance teams by presenting these topics to teammates so that they can understand, and similarly learning other processes and topics from teammates.
Outcome Assessment Strategies
Assessment of student performance in this course will be based on students ability to demonstrate knowledge and understanding of the required competencies, as determined through homework assignments, class participation, and examinations. Assignments will include problem sets, and also researching various aspects of a specific process. Class work will involve presentation of student research, and students will be tested on their ability to inform and learn from these presentations.
Course Content (Themes, Concepts, Issues and Skills)
1.0 Silicon planar technology
1.1 Describe how a capacitor, resistor, diode and MOSFET transistor work
1.2 Identify and relate the factors that control their performance
1.3 Explain how they can be made using planar technology
1.4 Draw cross sections and top views of these devices as made in silicon wafers
1.5 Describe the process flows that can be followed to make these devices
2.0 CMOS Design and Device Operation
2.1 Define CMOS.
2.2 Explain the advantages of CMOS technology in relation to other options.
2.3 Draw a cross-sectional view of a CMOS inverter circuit.
2.4 Draw a top view of a CMOS inverter circuit.
2.5 Draw the sequence of mask patterns for a CMOS inverter circuit.
2.6 Given a schematic diagram of a CMOS logic gate, analyze the operation of the logic circuit and construct a truth table that describes the operation of the circuit.
2.7 Given the schematic diagram for a CMOS logic gate, develop a process flow chart for the CMOS logic gate.
3.1 Explain four functions of silicon dioxide films in the manufacture of integrated circuits: surface passivation, doping barrier, surface dielectric, and device dielectric.
3.2 List the range of thermal SiO2 thicknesses used in VLSI processing for gate oxides and capacitor dielectrics, pad oxides, masking oxides and surface passivation oxides, and field oxides.
3.3 State the following properties of fused silica: DC resistivity, density, dielectric constant, dielectric strength, etch rate in buffered HF and melting point.
3.4 Write a description of the basic mechanism for the formation of SiO2 from Si using the linear-parabolic model.
3.5 Describe how the following factors affect oxidation rate: crystal orientation, dopants, source dependence, chlorine dependence, pressure, and plasma effects.
3.6 Describe dopant impurity redistribution during oxidation.
3.7 List the major parts and the function of each part in a furnace oxidation system.
3.8 Describe how oxide thickness can be measured by the optical interference method, ellipsometry, and capacitance methods.
4.1 List the ten basic steps in the patterning process used in VLSI manufacturing.
4.2 Identify the two primary functions that the photoresist layer performs.
4.3 Define the mathematical relationship between process factors, exposure wavelength and numerical aperture for resolution and depth of field.
4.4 Define the following terms: alignment, mask, and reticle.
4.5 Describe the optical, mechanical, chemical, and processing/safety properties of photoresist materials.
4.6 Compare and contrast positive and negative photoresist processing.
4.7 Compare and contrast the three major methods of optically transferring a pattern on a mask or reticle to a photoresist coated wafer: contact printing, proximity printing, and projection printing (1x and reduction).
4.8 Describe the process of making a mask or reticle.
4.9 Define the term "planarization" and state why planarization is used in VLSI processing.
4.10 List the common light sources used in projection printing systems and the wavelength of light produced by each source.
5.1 State the purpose or goal of the etch process in microelectronic fabrication.
5.2 Define the following terms: self bias, selectivity, etch rate, isotropic, and anisotropic.
5.3 Compare and contrast wet and dry etching processes.
5.4 Describe the chemical processes and problems involved in wet etching silicon dioxide, silicon nitride, and aluminum layers.
5.5 List six characteristics of a successful or useful etch process: (1) highly selective, (2) rapid, (3) uniformity across the wafer, (4) safe and clean, and (5) minimal damage to the substrate and (6) conducive to full automation.
5.6 List the six steps in an ideal dry etch process based solely on chemical mechanisms for material removal: 1.Reactive species generated in a plasma. 2. These species diffuse to the surface of the material to be etched. 3. Species are adsorbed on the surface. 4. A chemical reaction occurs, with formation of a volatile by-product. 5. By-product is desorbed from the surface. 6. The desorbed species diffuse into the bulk of the gas.
5.7 Describe the chemical reactions of etching the following film layers: silicon dioxide, polysilicon, refractory metal silicides and polycides, and metal layers.
5.8 Compare and contrast common dry etch equipment configurations.
5.9 Describe the following safety aspects of dry etching: working with compressed gases, working with toxic and/or corrosive gases, and safety design considerations in plasma etching equipment.
5.10 Describe the process of removing the photoresist layer.
6.1 State the purpose of the diffusion process in microelectronic fabrication.
6.2 State Fick's First and Second Law.
6.3 Describe the mechanism of diffusion in silicon using the vacancy model and the interstitial vacancy model.
6.4 Describe methods for measuring junction depths, sheet resistance, and diffusion profiles.
6.5 Determine the solid solubility and the diffusion coefficient of boron, phosphorus, and arsenic at a given temperature from a table.
6.6 List parameters that control the concentration of dopant at the surface of the wafer: concentration, diffusion coefficient, and temperature.
6.7 Compare and contrast the following methods of diffusion: horizontal versus vertical tube furnaces.
6.8 Describe the masking properties of silicon dioxide relative to diffusion.
7.0 Ion Implantation
7.1 List the five goals that need to be achieved for doping a wafer using ion implantation: (1) The species should be implanted in the exact quantity specified; (2) The implanted species should end up at the correct depth below the surface; (3) Implantation should be limited to only the designated areas of the substrate; (4) It should be possible to electrically activate the implanted impurities; and (5) The silicon lattice should be unchanged by the dopant incorporation process.
7.2 List the advantages and disadvantages of ion implantation over diffusion in doping the surface of a wafer.
7.3 List the major parts of an ion implanter and state the function of each part.
7.4 Define the following terms: channeling, annealing, and activation.
7.5 Describe the safety hazards associated with ion implanters.
7.6 Compare and contrast the doping profiles obtained using diffusion techniques and ion implantation techniques.
7.7 Describe the masking properties of silicon dioxide and photoresist relative to ion implantation.
7.8 Describe the use of rapid thermal processing to anneal wafers after ion implantation.
8.0 Chemical Vapor Deposition
8.1 Describe the mechanism of thin film growth: 1. Nucleation 2. Island stage 3. Coalescence
8.2 Describe the mechanical properties of thin films, e.g. adhesion and stress.
8.3 Describe the electrical properties of thin films: resistivity and permittivity.
8.4 List the six steps that are fundamental to all CVD processes. 1. Diffusion of gaseous reactants to the surface. 2. Adsorption of the reacting species on to surface sites. 3. Surface chemical reaction between the reactants. 4. Desorption of the reaction by-products. 5. Diffusion of by-products away from the surface. 6. Incorporation of the condensed solid product into the microstructure of the growing film.
8.5 Name four chemical sources of silicon that can be used commercially for epitaxial deposition.
8.6 List the major components of a commercial CVD system and state the function of each part.
8.7 Compare and contrast atmospheric pressure CVD reactors, LPCVD reactors, and PECVD reactors.
8.8 Describe the chemical reactions of CVD-deposited polysilicon.
8.9 Describe the chemical reactions for CVD SiO2 formation.
8.10 Describe the chemical reactions for CVD Si3N4 formation.
8.11 Describe the chemical reactions for tungsten deposition.
9.1 List four properties of a metal that make it a good choice for interconnecting devices on a wafer.
9.2 Define and describe the following problems of using pure aluminum as interconnects: junction spiking and electromigration.
9.3 Describe the following metallization processes: plating, evaporation, sputtering, and CVD.
9.4 Describe the major components of a sputtering system.
9.5 Compare and contrast metallization using evaporation and metallization using sputtering techniques.
9.6 State the safety hazards associated with evaporation and sputtering processes.
9.7 Describe the use of refractory metals and their silicides in VLSI fabrication.
9.8 Define the terms: eutectic and alloying.
9.9 Compare and contrast the purposes of annealing in ohmic formation versus ion implantation.
9.10 Describe the CVD process for silicides.
9.11 Explain why planarization steps are used between metallization steps.
10.0 Test and Packaging
10.1 Identify the following types of IC packages: dual-in-line package (DIP), pin grid array(PGA), and CERQUAD.
10.2 Describe eutectic and epoxy chip bonding techniques.
10.3 Describe the parametric and stress tests performed on each circuit.
10.4 List the major steps in the sort/test process.
10.5 List the major steps in the packaging process.